The invention relates to a phase locked loop.
A typical computer system uses clock signals to synchronize operations of digital circuitry of the system. Unfortunately, spectral components of these clock signals may radiate electromagnetic interference (EMI) emissions. For example, referring to FIG. 1, the spectral components of a clock signal might include a spectral component 10 that is located at a fundamental frequency (called fO and may be, for example, 100 MHz) of the signal as well as spectral components 12 that are located at harmonic frequencies (i.e., frequencies located at multiples of the fO frequency).
The EMI emissions may cause undesirable interference with the circuitry of the computer system and other electronic equipment near the computer system. To reduce the EMI emissions, the circuitry of the computer system may be housed inside a metal casing which prevents the EMI emissions from propagating outside of the casing. However, the casing often adds to the weight and cost of the computer system, and the casing has a limited shielding capability.
In addition to the casing, the EMI emissions may be further reduced by spread spectrum clocking (SSC) which reduces the energy peaks present in the spectral components of the clock signal. In SSC, a spread spectrum clock signal (called CLKIN (see FIG. 2)) may be generated by an SSC generator 14. To accomplish this, the SSC generator 14 might receive a signal (from a reference generator 13) which indicates a nominal fundamental frequency (called fNOM) for the CLKIN signal. The SSC generator 14 uses the fnoM frequency to generate the CLKIN signal which has, in place of a constant fundamental frequency, a time-varying frequency (called fSSC (see FIG. 3)) that deviates slightly (within 1 MHz, for example) about the fNOM frequency. As a result of the modulation of the fundamental frequency, spectral components 18 (see FIG. 1) of the CLKIN clock signal have typically smaller magnitudes than the corresponding spectral components 10 and 12 of the traditional clock signal, and as a result, the CLKIN signal typically generates fewer EMI emissions.
Referring to FIG. 3, over one cycle, the fSSC frequency may deviate about the FNOM frequency between a minimum frequency (called fL) and a maximum frequency (called fH). The fSSC frequency may, for example, resemble a sawtooth waveform 5 or may resemble a linear and cubic combination 7 of the sawtooth waveform 5. The frequency at which the fSSC frequency cycles is often called an SSC modulation frequency (called fM) of the CLKIN signal and may be higher than audio frequencies (20 Hz to 20 kHz frequencies) but significantly lower than the FNOM frequency. As examples, the fM frequency might be near 33 kHz, and the FNOM frequency might be near 100 MHz.
Referring back to FIG. 2, phase locked loops (PLLs) are often used to regenerate clock signals to minimize the effects of parasitic impedances of transmission lines that are used to communicate the clock signals. In this manner, a PLL 15 may receive and lock onto the CLKIN signal to generate another spread spectrum clock signal (called CLKOUT) that might ideally be a duplicate of the CLKIN signal.
However, referring to FIGS. 4 and 5, the CLKOUT signal is typically not an exact duplicate of the CLKIN signal but instead, may lead or lag the CLKOUT signal in time by a phase error, or clock skew (called TS). For purposes of the following description, the clock skew TS is defined as an interval of time in which the CLKIN signal undesirably leads the CLKOUT signal and might assume a negative (when the CLKIN signal lags the CLKOUT signal) or a positive (when the CLKIN signal leads the CLKOUT signal) value.
As an example, one SSC modulation cycle, the fSSC frequency (see FIG. 3) periodically decreases (during time T1 to time T2, for example) from the fH to the fL frequency to produce a resultant skew TS 20 (see FIG. 6) that approaches a large negative value (a value near xe2x88x921000 picoseconds (ps), for example). Thus, during this time interval, the CLKIN signal may lag the CLKOUT signal due to the decrease in frequency. Once the fSSC frequency reaches the fL frequency (at time T2, for example) and then abruptly changes course and rises upwardly (after time T2, for example) toward the fH frequency, the skew TS 20 may approach a large positive value (1000 ps) due to the increase in frequency and the PLL""s temporary over compensation.
One way to decrease the skew is to increase the response speed of the PLL 15, and one way to increase the response speed of the PLL 15 is to increase the PLL""s bandwidth. For example, the large skew TS 20 may occur when the PLL 15 has a relatively low bandwidth (a bandwidth of 440 kHz, for example), but when the PLL 15 has a larger bandwidth (a bandwidth of 1.2 MHz, for example), a resultant skew TS 21 (see FIG. 6) may be much smaller (the skew TS may deviate between 140 and xe2x88x92140 ps, as an example). However, even with this reduction, the skew TS 21 may not be sufficient to satisfy timing requirements of the computer system.
Thus, there is a continuing need for an arrangement to reduce the skew of such a system.
In one embodiment, a method includes locking onto a phase of a spread spectrum clock signal to minimize a phase error between an output clock signal and the spread spectrum clock signal. The spread spectrum clock signal has a time-varying frequency that cycles at a modulation frequency, and the spread spectrum and output clock signals are approximately separated by the phase error. The method includes minimizing a phase angle between spectral components of the output and spread spectrum clock signals near the modulation frequency.
In another embodiment, a phase locked loop minimizes a phase error between a spread spectrum clock signal and an output clock signal. The phase locked loop includes a detector and a filter. The detector receives a spread spectrum clock signal and compares the spread spectrum clock signal with an output signal. The spread spectrum clock signal has a time-varying frequency that cycles at a modulation frequency. The filter is coupled to the detector to minimize a phase angle between spectral components of the output and spread spectrum clock signals near the modulation frequency.